1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device including a multi-layer interconnect structure.
2. Description of the Related Art
Recently, copper has come to be more popularly used as a material of an interconnect of a semiconductor device, because of its low specific resistance. Since it is difficult to perform reactive ion etching on copper, the damascene process is usually employed for forming the interconnect when using copper as the interconnect material. The damascene process includes a single damascene process in which an interconnect layer and a via plug are sequentially formed, and a dual damascene process in which both the interconnect layer and via plug are formed at a time. Among these processes, the dual damascene process, disclosed in JP-A No.2000-91425 for example, is more advantageous from a viewpoint of simplifying manufacturing steps.
The dual damascene process for forming an interconnect structure includes so-called “via first” approach and “trench first” approach. The “via first” approach represents a process of forming a via hole portion first, and then forming a trench for the interconnect over the via hole portion in accordance with the via hole pattern. On the other hand, the “trench first” approach means a process of forming the trench for the interconnect first and then forming the via hole according to the trench pattern. Of these approaches, the former is more advantageous from a viewpoint of assuring correct performance of the via hole as a contact. Now referring to FIGS. 1A to 4B, conventional “via first” steps of the dual damascene process will be described below.
First, a lower interconnect layer 1 is formed in a predetermined pattern on a silicon substrate, which is not shown in the drawings (FIG. 1A). A copper-diffusion barrier 2 consisting of silicon nitride (SiN) is formed over the substrate, and an interlayer dielectric film 3 consisting of silicon oxide (SiO2) is formed over the copper diffusion barrier 2 (FIG. 1B). Then a via hole 4 is formed on the interlayer dielectric film 3 by lithography and etching (FIG. 1C).
Then spin coating of an organic substance is performed to form an anti-reflection coating 5 all over the substrate including the via hole. At this stage, the anti-reflection coating 5 is formed in a greater thickness inside the via hole than over a surrounding flat region, because the material pools inside the via hole during the spin coating process (FIG. 2A).
A resist layer 6 is formed over the anti-reflection coating 5 (FIG. 2B), after which an opening is formed around the via hole 4 by exposure through a photo mask defining an upper interconnect pattern followed by alkaline development, so that a resist pattern is formed (FIG. 2C). Then a portion of the anti-reflection coating 5 and of the interlayer dielectric film 3 exposed inside the opening formed as above are sequentially removed by etching, through the resist layer 6 with the opening utilized as a mask. As a result, an interconnect trench is formed at an upper portion of the via hole (FIGS. 3A, 3B). After that, copper is buried in the via hole and the interconnect trench, and finally the lower interconnect, the upper interconnect and the via connecting the interconnects are formed through CMP (chemical mechanical polishing) process for removing copper existing in a region outside the opening.
However, in the conventional process, a cylindrical projection is prone to be formed in the interconnect trench, as shown in FIGS. 3A and 3B. The reason of appearance of such projection will be explained in the following.
When starting the etching of the interconnect trench, the anti-reflection coating and the resist layer are filled inside the via hole. These layers are made of different materials, therefore the etching rate is also different with the respective layers during the etching process of the interconnect trench. Accordingly either layer having a slower etching rate remains unremoved with the progress of the etching process, finally forming a relatively projecting portion. In general, the anti-reflection coating is less sensitive to etching than the resist layer in the etching process of the interlayer dielectric film, in which case the anti-reflection coating 5 remains in a cylindrical shape around a sidewall of the via as shown in FIG. 3A.
Now, since the sidewall of the via is slightly tapered, a portion of the interlayer dielectric film 3 hidden under the cylindrical projection tends to be left unremoved by etching. Consequently, the interlayer dielectric film 3 remaining at this point forms a projection (FIG. 3B). Such projection is bent (FIG. 4A) as a result of a subsequent ashing process for removing the resist layer 6, and the bent portion disturbs an adequate step coverage during the burying process of the interconnect material, thereby causing a faulty deposition of a barrier metal 25 (FIG. 4B). Also, in case of forming a copper layer by plating, a copper seed layer is also prone to cause a similar faulty deposition.